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Next Generation of SoC Design: From Atoms to Systems
April 23rd 2019 | 10:00 am - 11:00 am (PDT)

This webinar provides examples of how complex new technologies such as Flash memory, other advanced non-volatile memory technologies, and complex SoCs (such as Nvidia’s Xavier and Apple’s A12), use and re-use design IP at the architectural level, but require specialized new IPs that need to be simulated and analyzed down to the nanometer and atomic levels.


Unraveling and Optimizing Transistor-Level Simulation
April 24th 2019 | 18:00 - 19:00 (PDT)

Circuit Simulation is one of the most critical parts of the design process. Validating circuit behavior is essential to saving cost, minimize turn-around times and establishing reliable system characteristics before IC manufacture.


Managing Design Technology Co-Optimization (DTCO) Using One Command File
April 30th 2019 | 10:00 am - 11:00 am (PDT)

This webinar illustrates the advantages of using a single command file and a GDSII layout to create an entire Design Technology Co-Optimization (DTCO) experiment set, using physics-based 3D active devices and Back End Of Line (BEOL) interconnect cell level structures, for extraction of the active device Spice model parameters and extracted RC parasitics using a 3D field solver, and for final Spice circuit simulation


Accelerate Custom Layout Editing with Expert and JavaScript
May 2rd 2019 | 10:00 am - 11:00 am (PDT)

This Webinar will provide a discussion about the basics of the JavaScript API used to customize Expert.