Volume 27, Number 2, April - May - June 2017

Effect of Fin Thickness on Subthreshold Characteristics of 10 nm FinFETs Using 3D TCAD

The planar bulk Si metal-oxide semiconductor field-effect transistor (MOSFET) has reached its scaling limit due to various short channel effects (SCE). With 20 nm advanced planar technology, the source and drain encroached into channel resulting in off state leakage current.



3D Simulation of Dual-Gate Thin Film Transistors

In this article, we demonstrate that our 3D TCAD simulation framework, Victory, can simulate a normal DGTFT and an L-shape DGTFT [2] in 3D accurately, robustly and in a reasonable simulation time.


Edge Effect Analysis on TFT Devices Using 3D Numerical Simulation

We present the simulation results for the four different edge shapes by 3-dimensional analysis using Victory Process and Victory Device, and we show the influence of the edge profiles on the electrical characteristics.




Model Extraction for Body-Biased XDMOS Devices

This paper illustrates a model extraction methodology for body-biased extended drain MOSFET (XDMOS) devices, using the standard compact HVMOS model HiSIM_HV2, Version 2.3.1.