SURGE Shenzhen

Silvaco announces the launch of a Silvaco Users Seminar at various Silvaco sites in 2018.

SURGE (Silvaco UseRs Global Event) is a premier and unique event that brings together both the EDA as well as the IP community to discuss new technologies, smart integration for innovative applications and new techniques for realizing advanced designs.

  • Live demos of new features and capabilities
  • Unique variety of technical presentations
  • Roadmap presentations and exciting technology updates
  • Dynamic panel discussions and executive keynotes
  • Networking opportunities with industry experts

Silvaco China will be hosting SURGE on July 26, 2018. Please save the date. We will be in touch with details on the sessions and tracks including information on our keynote speaker.

Time:

  • July 26, 2018 12:30 - 6pm

Venue:

  • The Westin Shenzhen Nanshan
    9028-2 Shennan Ave, RenMin NanLu, Nanshan Qu, Shenzhen City
    Guangdong Province, China, 518053

Agenda

Time
12:30 - 13:00 Registration
13:00 - 13:10 Welcome Presentation - Sharon Fang
13:10 - 13:40 Company Update - David L. Dutton
13:40 - 14:10 Challenges For High Resolution AMOLED Displays - Guan Zhen Peng
AMOLED continues to draw attention for the flat panel display because of its advantages over other displays. Higher resolution, smaller form factor and lower power consumption are three main requirements in the mobile displays, which needs faster development and manufacturing capability to meet these requirements for AMOLED displays. In this presentation, Tianma would like to share the latest updates to meet the market needs. Moreover, the risks and trade-offs to reach a higher resolution AMOLED displays with full-screen feature will also be discussed.
14:10 - 14:40 3D RC Extraction For Advanced FinFET - Francis Benistant
14:40 - 15:00 Coffee Break

Time Session 1 – Display
15:00 - 15:30 Multi-level Co-design for Low Power AMOLED Displays with Compensation of Luminous Non-uniformity - Xiaojun Guo
Active matrix organic light emitting diode (AMOLED) displays with a thinner and simpler structure compared to LCDs provide a set of attractive attributes to be used for high-quality video applications. With the development of efficient and stable organic light emitting diodes (OLEDs) and low temperature polycrystalline silicon (LTPS) thin film transistors (TFTs), the commercialization of AMOLED display products is accelerating with rapidly expanding their market share for small-sized mobile applications since their mass production launch in 2007. Different from the LCDs, which are voltage driven devices, OLEDs are current-driven. Therefore, compared to the one thin-film transistor (TFT) and one capacitor (1T-1C) pixel circuit used in AMLCDs, the pixel circuits for AMOLED displays require at least one additional TFT as the current source or sink to provide the constant current for OLEDs. In practical cases, more complicated pixel circuits as are required to compensate the spatial or temporal luminance variations caused by processes or long-time device operation induced electrical performance variations of the driving TFT and the OLED devices. On the other hand, for battery powered mobile applications, low power consumption is important to increase operating lifetime, and decrease the system weight and volume for the less required capacity of the battery. Especially, with the increase of the display resolution and incorporation of more and more attractive functions into the mobile electronics system, the combined effect of more power consumption and extended usage has caused the rate of power consumption to outpace the limited improvement in battery power density. To address these issues, device/circuit/system multi-level co-design and optimization is very important. This talk will provide examples of using TCAD, SPICE and system-level simulation approaches to investigate the design techniques at the different levels.
15:30 - 16:00 Hysteresis Model Development for AMOLED Technology - WS Lee
The AMOLED technology are very sensitive due to hysteresis problems
To suppress this kinds of problems, It need to reproduce the hysteresis behavior with circuit simulator.
We proposed the hysteresis model, which are take into account oxide trapping charge induced vth shift and interface trap induced vth shift.
The hysteresis model will be optimized based on real experimental data, which is measured with high resolution equipment.
Then it reproduced the OLED current deviation with AMOLED 7T1C circuit of chess board signal stimulus due to hysteresis..
16:00 – 16:20 Coffee Break
16:20 - 16:50 Silvaco TCAD Simulation for AMOLED Technology - Kevin Chang
AMOLED technology have attracted more and more attention recently. So the TFT and OLED device behaviors are need to deeply investigated to achieve best performance for the display market. On the TFT part, the degradation behavior of the device is becoming more important issue in the application. In this talk we will present the simulation of PBTS, NBTS of TFT device to investigate and understand the physical mechanics, so to improve the device performance. On the OLED device part, we need to investigate the electrical and optical behaviors, which will be presented too in this talk.
16:50 - 17:20 Accurate RC extraction for realistic 3D interconnect structures - Hongyi Yu
When the process node becomes smaller and smaller, the parasitic effects becomes more and more serious in the circuits. So accurately extract the parasitic capacitance and resistance has become more and more important. However, for most of the RC extractors in the market, accuracy is the major problem for complex chips such as deep sub-micron CMOS, FinFET, MEMS, and TFT devices. Clever can extract RC on any complex interconnect structures with any user requested accuracy by field solving the physical mathematical equations adaptively. So to build an effective and robust electronic device, Clever is a must have tool.
17:20 - 17:50 Accelerate Time-to-Market For Your Designs with Expert FPD - Yusuke Ito
Expert is an Analog Layout Editor which has reputation for its displaying speed and is used by a great number of users. However, so far it was not suited for FPD designs deals with large layout areas compared to normal analog IC designs, and lines of any angles. This time, new wire creation/editing functions for FPD designs were added with the cooperation from one of our FPD customers. In addition, the improvement for its basic editing operation method was also made. Its processing speed for some features for designing FPD has also been improved. Therefore, it has a significant efficiency improvement for designing FPD layout, which is expected to shorten the time of so-called Time-to-Market. In this session, the details of these updates will be presented.

Time Session 2 – IC
15:00 - 15:30 Methods to Simulate and Optimize the Performance of Power Devices Using TCAD - Eric Guichard
Silicon has long been the semiconductor of choice for high-voltage power electronics applications. However, wide-bandgap semiconductors such as SiC and GaN have begun to attract attention because they are projected to have much better performance than silicon. We will review during this talk, advancement made from a simulation point of view to simulate Silicon and non-Silicon power devices, including SiC and GaN process simulation, TCAD to spice flow, single Event burnout Electro-Thermal simulation of SEEs and Split-Gate Trench UMOSFET.
15:30 - 16:00 Standard Cell Layout Migration and Optimization - Guilherme Schlinker
This talk will present an efficient methodology for migrating and optimizing standard cell libraries. Foundation IP reuse through migration between non-disruptive technology nodes can save a lot of engineering resources and provide an initial basis for further optimization of layouts in the target technology. In this presentation we will demonstrate how a standard cell library can be migrated using a 2-D compaction engine combined with static geometrical transformations. We will also show how layouts can be further optimized for Automotive or DFM rules with customization of the compaction rules.
16:00 – 16:20 Coffee Break
16:20 - 16:50 RC Reduction to Speed Up Simulation - Ke Liu
16:50 - 17:20 Building Next Generation SoC’s with Silvaco IP - Warren Savage
Silvaco has amassed a portfolio of more than 100 silicon-proven IP cores in less than 2 years. Hear about Silvaco’s leading edge IP solutions for the China market and how we can be your trusted partner for building your next generation of SoC products.
17:20 - 17:50 High-Sigma Design with VarMan - Thomas Blaesi
Process variability at advanced technology nodes has become a key challenge for IC designers. A new generation of tools are required that provide efficient and reliable solutions for analog, RF, standard cells, IO and memory designers. A comprehensive suite of analysis tools that allow the designer to accurately address statistical process variations and to make the right design decision upfront is needed. The tools need to ensure that designers do not need to be expert statisticians to understand and optimize the impact of process variations on their design.
17:50 - 19:00 Lucky Draw and Cocktail Time

*Tracks and times are subject to change without notice.

Surge Highlights:

Sharon Fang
Welcome Presentation Sharon Fang
General Manager, Silvaco China

Sharon Fang is a seasoned executive with a distinctive combination of sales, marketing, strategic thinking and operational skills, successful track record and driving revenue growth as both an individual contributor and sales manager in EDA. Sharon currently serves as General Manager for Silvaco China. In her role as head of China region, Sharon is putting together the necessary processes and infrastructure to streamline the sales process, empowering individuals and teams to maximize value to customer as well as ROI. The China organization is focused on helping drive customer success through the use of Silvaco TCAD-to-sign off solutions, modeling services, IP management & compliance software while driving business growth for the company.
Sharon holds a bachelor of Art degree from Southwest China Normal University and an MBA degree from Saint Mary’s College of California.

David L. Dutton
Technology Updates from CEO CEO, David L. Dutton
Silvaco, Inc.

David L. Dutton serves as Chief Executive Officer of Silvaco and is also a member of the company’s Board of Directors. He has also served as an advisory board director of solar company Sunpreme since 2013 and LED manufacturer Glo since 2014. Dutton serves as managing principal of business management consulting firms SemiEnergy and CEO to CEO and was an active member of the Silicon Valley Leadership Group and the Alliance of Chief Executives.
From 2001 to 2013, Dutton served as President, CEO and board director member of Mattson Technology, where he led the company's turnaround to profitability and quadruped the company's total available market by expanding into new semiconductor and clean tech capital equipment markets. Prior to joining Mattson, Dutton held management, engineering and product positions at Silicon Valley technology companies, including Intel and Maxim Integrated Products. Dutton holds a B.S. in Geology from San Jose State University.

Challenges for High Resolution AMOLED Displays Guan Zhen Peng
Tianma Micro R&D Director

Dr. Peng has been in the LTPS field since 1998 when he was a Ph.D student. From 1998 to 2003, he devoted himself to the LTPS process as well as novel device structure to enhance the TFT performance for flat panel display applications. From the 2004, Dr. Peng has been working in AMOLED industry globally (Taiwan, Japan and China) and has been responsible for the development of AMOLED technologies as well as the production of AMOLED products.

Xiaojun Guo
Multi-level Co-design for Low Power AMOLED Displays with Compensation of Luminous Non-uniformity Xiaojun Guo
Professor, Shanghai Jiaotong University
Dr. Xiaojun Guo leads the Printed Electronics and Flexible Integration (pEFi) research lab for the future sustainable and intelligent society of “internet of everything”. Dr. Guo has authored more than 60 technical papers in international journals, and given more than 20 invited talks in international conferences organized by IEEE/SID/ECS/SPIE societies
Dr. Xiaojun Guo received his first degree in electronic engineering from Jilin University, and Ph.D. degree in electronic engineering from University of Surrey, Guildford. Before joining Shanghai Jiao Tong University, he worked in Plastic Logic Ltd.

Won-Seok Lee
Hysteresis Model Development for AMOLED Technology Won-Seok Lee
Sr. Application Engineer, Silvaco Korea.
Won-Seok Lee is Senior Applications Engineer at Silvaco Korea.He has over 20 years of experience in the simulation division including modeling, and device physics.
With responsibilities including Technical device theory and support of Silvaco EDA customers for a wide variety of applications.
Additionally, He dedicating to develop the dynamic models for SPICE.

Kevin Chang
Silvaco TCAD Simulation for Technology Kevin Chang
Application Engineer, Silvaco, Inc.

Kevin Chang has worked in TCAD area in semiconductor and display market more than 10 years, and has lots of experience to support customer to succeed in process and device simulation and 3D physical parasitic extraction tool.


Hongyi Yu
Accurate RC extraction for realistic 3D interconnect structures Dr. Hongyi Yu
Senior Engineering Manager, Silvaco

Dr. Hongyi Yu has been with Silvaco since 1999. He is the key architect and developer of Clever. He served as a staff scientist, engineer manager, principle engineer and senior engineer manager within Silvaco. Before joining Silvaco, he was a post doctor and research associate at Rensselaer Polytechnic Institute. He holds a Ph.D degree in Applied Mathematics from Tulane University.

Yusuke Ito
Accelerate Time-to-Market For Your Designs with Expert FPD Yusuke Ito
Application Engineering, Silvaco

Yusuke Ito is in-charge of Silvaco’s Back-End EDA tools (Layout Editor, Parasitic Extraction, Verification) and currently working with variety of customers in Japan. Before joining Silvaco, he was a designer of Renesas System Design for 10 years and gaining extensive experience in back-end design particularly digital layout. He obtained his Master's degree of Engineering, Majoring in Communications and Integrated Systems from Tokyo Institute of Technology.

Eric Guichard
Methods to Simulate and Optimize the Performance of Power Devices Using TCAD Dr. Eric Guichard
Vice President of the TCAD Division, Silvaco

Dr. Eric Guichard is Vice President of Silvaco’s TCAD Division. He is responsible for managing all aspects of the TCAD division from R&D to field operations.


Guilherme Schlinker
Standard Cell Layout Migration and Optimization Guilherme Schlinker
Director of Layout Automation, Silvaco

Guilherme Schlinker is Director of Layout Automation at Silvaco. He is responsible for Silvaco’s Layout Optimizer Product Line. Prior to joining Silvaco in 2018 he worked for 12 years at Nangate, where he developed EDA tools for layout automation and delivered standard cell library IP for multiple foundries and technology nodes. He joined Silvaco as part of the acquisition of Nangate and continues working with the former Nangate products. Mr. Schlinker holds a Computer Engineering degree from Universidade Federal do Rio Grande do Sul, Brazil.

Warren Savage
Building Next Generation SoC’s with Silvaco IP Warren Savage
General Manager, IP, Silvaco

Warren Savage serves as the General Manager of Silvaco’s newly formed IP Division. He has spent his entire career in Silicon Valley with engineering and management roles in leading companies including Fairchild Semiconductor, Tandem Computers, Synopsys, and most recently with IPextreme.
He is a widely recognized expert in the field of semiconductor intellectual property and with building IP businesses beginning with Synopsys (DesignWare) in 1995 and the founding of IPextreme in 2004, which was acquired by Silvaco in 2016.
Warren holds a BS in Computer Engineering from Santa Clara University and an MBA from Pepperdine University.

Thomas Blaesi
High-Sigma Design With VarMan Thomas F. Blaesi
Vice President, Global Marketing

Thomas F. Blaesi is Vice President of the global marketing group, which is chartered with defining, driving, and promoting Silvaco’s leadership in the TCAD, EDA and IP market. Key areas of responsibility include strategic planning, corporate marketing, product marketing, market research, brand management, corporate communications, and ecosystem alliance programs.
Thomas joined Silvaco in October 2017 with more than 25 years of experience in corporate strategy, business development, and marketing in semiconductor, and electronic design automation industries. He has led major projects in SoC platform-based design, system-level design, and design for manufacturing in addition to hands-on experience in custom and semi-custom chip design and development.
Most recently, Thomas was the managing partner at Zeema Technologies. Before that, he served as CEO of Chipvision, and held various senior business and technical positions at Cadence, Synopsys, and LSI Logic.
Thomas holds a BS in electrical engineering and computer science from Hochschule Furtwangen University, Germany.

Francis Benistant
3D RC Extraction For Advanced FinFET Francis Benistant
Manager of the Global TCAD group, GlobalFoundries
Francis Benistant received his PhD in 1996 from the Institute National Polytechnique de Grenoble (INPG) in France, working at the LETI research center. Between 1996 and 2000, he worked as a device and TCAD engineer in the USA and Switzerland. Between September 2000 and June 2018, he was the manager of the Global TCAD group in GlobalFoundries.

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