Silvaco To Showcase Advanced Node Solutions At DAC 2016

Silvaco technology experts will be available to discuss and demo our TCAD-to-signoff solutions with emphasis on new products and capabilities serving advanced process nodes.

  • FinFET RC parasitic extraction - MEOL/BEOL parasitics are critical at FinFET nodes and detailed analysis via 3D field solvers is required to accurately capture parasitic effects
  • OA iPDK support - iPDK support simplifies access to Silvaco’s custom design flow which are ideally suited for IoT process nodes, but are also being used at the most advanced nodes such as for 10nm analog IP development
  • Quick IR drop and EM analysis product used during layout to catch issues such as missing vias
  • FastSPICE for fast functional verification of SRAM and analog blocks that is becoming a significant challenge due to large extracted netlists at double patterned process nodes
  • Fully automated characterization of setup and hold for critical timing arcs for large extracted SRAMs
  • Variation analysis inclusive of Fast Monte Carlo, Statistical corners and High Sigma analysis for analog and memory designs
  • Statistical functional verification of standard cell libraries with reduction in time taken from weeks to days


Silvaco continues to collaborate with EDA and IP ecosystem partners some of whom will be presenting their solutions at our booth:

  • IPextreme
    • Together with its Constellations partners will showcase a broad portfolio of silicon-proven microprocessor, SoC infrastructure, automotive, and ESD/IO cores. In addition they will be demonstrating their latest IP management and IP compliance software.
  • Fieldscale
    • Will showcase parametric simulation of projected capacitive touchscreens, varying in controller, electrode pattern and dimensions, for several finger positions, parametric analysis of the effects of trace clearance and voltage level on the electric field in PCBs, and electrostatic simulation in ICs considering Line Edge Roughness (LER)
  • Coupling Wave Solutions
    • Will showcase early noise analysis capability used in CMOS/FDSOI technologies and fast SOI substrate noise and parasitic analysis that shrinks RF design time on SOI technologies

Partner Presentations

Silvaco continues to collaborate with customers, partners and industry consortia to address and solve advanced technology challenges, and our participation and demonstrations in partner booths include:

  • TSMC OIP Theater at Booth #848
    • Monday, June 6th at 4 :00 PM
    • Tuesday, June 7th at 5:15 PM
    • Wednesday, June 8 at 11:30 AM
  • SI2 Pavilion, Booth #239
    • Building Successful OpenAccess Applications, And Avoiding Bumps in the Road - Tuesday, June 7 at 2:00 PM
    • Minalogic Showcase - Tuesday, June 7 at 4:00pm-6:00 PM

 

Cilck here to schedule a time to meet with the Silvaco team