Application Notes

Digital CAD

• 4-012 - AccuCore STA DSPF Backannotation Timing
• 4-011 - Automatic Generation of Configuration Files for AccuCell
• 4-010 - Using the Verilog (PLI) Interface in Silos-X/Harmony on Windows
• 4-009 - Understanding the AccuCore Work Flow and Processing Options
• 4-008 - How to Define Optimal Slopes & Loads for Cell Characterization
• 4-007 - Automatic Port Determination in Catalyst
• 4-006 - Characterize I/O Cells Using AccuCell
• 4-005 - LINT Your Design with SILOS-X
• 4-004 - SILOS-X Code Coverage
• 4-003 - Using PLI to Implement a User Defined System Task for Use with SILOS-X and Harmony
• 4-002 - Manual Latch & Flip-Flop Recognition in AccuCell and AccuCore
• 4-001 - Latch & Flip-Flop Modeling in AccuCell and AccuCore