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홈
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TCAD
Process Simulation
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Digital CAD
다운로드 및 기술지원
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셀 라이브러리 특성화, 대규모 코어 STA, Verilog 시뮬레이션 및 장애 분석을 위한 디지털 툴
Rev. 081109_06
브로셔 (PDF) 1.5 MBProduct Group:
SILOS
Verilog Simulator
Verilog Simulator
HyperFault
Mixed-Level Fault Simulator
Mixed-Level Fault Simulator
AccuCell
Cell Characterization and Modeling
Cell Characterization and Modeling
AccuCore
Block Characterization and Modeling With STA
Block Characterization and Modeling With STA
CatalystAD
SPICE Netlist to Verilog Gates Converter
SPICE Netlist to Verilog Gates Converter
CatalystDA
Verilog Netlist to SPICE Netlist Converter
Verilog Netlist to SPICE Netlist Converter
Spider
Place and Route Design Flow
Place and Route Design Flow