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Spider:

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90 Day | 1 Year | 3 Year

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Spider is a netlist-to-GDSII place and route design flow for mainstream physical design and implementation. Spider can be used as a replacement for Synopsys Astro, Synopsys IC Compiler (ICC), Synopsys ZRoute, Cadence First Encounter, Cadence SoC Encounter, Cadence NanoRoute, Magma Talus Vortex, Mentor Olympus-SoC and AtopTech APRISA providing the following key features:

• Self-Checking Correct-by-Construction physical layout with n-layer design capabilities supports gate-array, structured-ASIC and standard-cell SoC design styles
• Imports and exports VERILOG netlist, Liberty (.lib) timing library, LEF/DEF physical and technology library and design exchange format data with a seamless interface to third-party logic synthesis, physical synthesis and place-n-route tools like (Synopsys Astro, Synopsys IC Compiler (ICC), Synopsys ZRoute, Synopsys Design Compiler (DC), Synopsys Design Compiler Topographical (DCT), Cadence Encounter RTL Compiler, Cadence Encounter RTL Compiler with Physical, Cadence First Encounter, Cadence SoC Encounter, Cadence NanoRoute, Magma Talus Design, Magma Talus Vortex, Mentor Olympus-SoC and AtopTech APRISA)
• Automatic utilization, aspect ratio, design partitioning, region control, net-length & 2D routing congestion driven cell and macro placement optimization for mixed free-form and datapath-like styles with "what-if" floorplanning analysis of multiple physical cell-types with weighted flylines
• Automatically generate chip padframe with macro and core power planning and rectilinear blocks with pin boundary optimization and constraints
• Automated and interactive contour, embedded block, ring, strap and rail power, ground and rip-up and re-route signal routers with real-time netlist & design rule enforced layout and ECO with independent on-line verification
• Automatically optimizes insertion delay, skew and inter-clock skew during Clock Tree (CT) and High Fanout Net (HFN) Synthesis providing delay, transition, skew and load net details from embedded SPICE and RC extraction engines
• Seamless interface with Silvaco EXPERT, Silvaco HIPEX-RC

Synopsys Astro, Synopsys IC Compiler (ICC), Synopsys ZRoute, Cadence First Encounter, Cadence SoC Encounter, Cadence NanoRoute, Magma Talus Vortex, Mentor Olympus-SoC and AtopTech APRISA are trademarks of their respective owners.