AccuCore

90 Day Development Roadmap

AccuCore STA

• Enhance support for buses and bus-pins in hierarchical Verilog netlists
• Enhance SDF import to permit merging incomplete timing definitions
• Generate SDF forward annotation path timing constraints
• Generate Synopsys NET format net timing constraints
• Expand SDF generation to output full gate level regression backannotation timing

Last Revised 2/27/2012