SmartSpice

3 Year Development Roadmap

Core

• Develop Single Electron Transistor (SET) model
• Develop RC linear reduction method using PACT algorithm

Models

• Develop model libraries for hardware accelerated (FPGA, GPU) processing architectures

Verilog-A

• Develop multiple matrices support for circuit simulation with high and low frequency analog content [RE-WRITE]

HSPICE compatibility

• Exploration Block for optimum circuit design

Spectre compatibility

• Nonlinear sensitivity analysis

FineSim compatibility

• Fast Monte Carlo option
• Multi rate multiprocessing simulation algorithm

SmartView

Core

• Advanced post processing for digital and mixed-signal simulations:
  
  • Precision on digital marker
  • Digital vector radix selection
  • Digital chart preview or horizontal scrollbar
  • Digital signal search to change
  • Scroll digital chart to a marker
  • Scroll digital chart to a time point
  • Digital marker resolution restricted to simulation maximum precision
  • Add digital display groups
  • Add digital chart signal/group reordering
  • Digital chart Add Blank/One/Zero traces
  • Digital chart rename trace
  • Mark multiple signal changes on digital charts
  • Digital chart scan to value
  • Digital chart expression display
  • Digital chart display, analog signals as digital
  • Digital chart, go to signal definition
  • Digital chart, display source line for a signal change
  • Digital chart drag and drop signals from source window
  • Digital chart trace feature
  • Digital chart signal name horizontal scroll

FineWave compatibility

• Clock jitter measurement on Eye Diagram

WaveView compatibility

• Design oriented measurement utilities for Memory, PLL, DSP, ADC, and DAC
• Support for WSF ASCII/binary and PSPICE-DAT formats

Last revised 3/6/2012